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quad, 12 - bit, 40/65 msps serial lvds 1.8 v a/d converter ad9228 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may resul t from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006C 2010 analog devices, inc. all rights reserved. features 4 adcs integrated into 1 package 119 mw adc power per channel at 65 msps snr = 70 db (to nyquist) enob = 11.3 bits sfdr = 82 dbc (to nyquist) excellent linearity dnl = 0.3 lsb (typical) inl = 0.4 lsb (typical) serial lvds (ansi - 644, default) lo w power , reduced signal option (similar to ieee 1596.3 ) data and frame clock outputs 315 mhz full - power analog bandwidth 2 v p - p input voltage range 1.8 v supply operation serial port control full - chip and individual - channel power - down modes flexible bit orientation built - in and custom digital test pattern generation programmable clock and data alignment programmable output resolution standby mode applications medical imaging and nondestructive ultrasound portable ultrasound and digital beam - forming syste ms quadrature radio receivers diversity radio receivers tape drives optical networking test equipment general description the ad9228 is a quad, 12 - bit, 40/65 msps analog - to - digital con - verter (adc) with an on - chip sample - and - hold circuit designed for low c ost, low power, small size, and ease of use. the product operates at a conversion rate of up to 65 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl -/ cmos - /lvds - compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate l vds serial data rate. a data clock output (dco) for functional block dia gram serial lvds ref select + ? a d9228 agnd vi n ? a vi n + a vi n ? b vi n + b vi n ? d v i n + d vi n ? c vi n + c sense vref avdd dr vdd 12 12 12 12 pdwn reft refb d ? a d + a d ? b d + b d ? d d + d d ? c d + c fco? fco+ dco+ dco? cl k+ dr gnd cl k? serial port interfa ce csb scl k/dtp sdi o/odm rb ias serial lvds serial lvds serial lvds pipe li ne adc pipe li ne adc pipe li ne adc pipe li ne adc data rate multip li er 0.5v 05727-001 figure 1. capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. individual - channel power - down is su pported and typically consumes less than 2 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern g eneration. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi ). the ad9228 is available in a n rohs compliant , 48 - lead lfcsp. it is specified over the industrial temperature range of ?40 c to +85 c. product highlights 1. small footprint. four adcs are contained in a small, space - saving package . 2. l ow power of 119 mw/channel at 65 msps. 3. ease of use. a data clock output (dco) is provided that operates at frequencies of up to 390 mhz and supp orts double data rate (ddr) operation. 4. user flexibility. the spi control offers a wide range of flexible features to meet specific system requirements. 5. pin - compatible family. this includes the ad9287 (8 - bit), ad9219 (10 - bit), and ad9259 (14 - bit).
ad9228 rev. d | page 2 of 56 table o f contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 ac specifications .......................................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 7 timing diagrams .............................................................................. 8 absolute maximum ratings .......................................................... 10 thermal impedance ................................................................... 10 esd caution ................................................................................ 10 pin configuration and functi on descriptions ........................... 11 equivalent circuits ......................................................................... 13 typical performance characteristics ........................................... 15 theory of operation ...................................................................... 20 analog input considerations ................................................... 20 clock input considerations ...................................................... 23 serial port interface (spi) .............................................................. 31 hardware interface ..................................................................... 31 memory map .................................................................................. 33 reading the memory map table .............................................. 33 reserved locations .................................................................... 33 default values ............................................................................. 33 logic levels ................................................................................. 33 evaluation board ............................................................................ 37 power supplies ............................................................................ 37 input signals ................................................................................ 37 output signals ............................................................................ 37 default operation and jumper selection settings ................. 38 alternative analog input drive configuration ...................... 39 outline dimensions ....................................................................... 53 ordering guide .......................................................................... 53
ad9228 rev. d | page 3 of 56 revision history 4 /10 rev. c to rev. d changes to table 16 ........................................................................ 35 updated outline dimensions ........................................................ 53 changes to ordering guide ........................................................... 53 12/09 rev. b to rev. c updated outline dimensions ........................................................ 53 changes to ordering guide ........................................................... 54 7/07 rev. a to rev. b changes to figure 3 ........................................................................... 7 change to table 7 ............................................................................ 10 5/07 rev. 0 to rev. a changes to features .......................................................................... 1 change to effective number of bits (enob) ................................ 4 changes to logic output (sdio/odm) section .......................... 5 added endnote 3 to table 3 ............................................................. 5 changes to pip eline latenc y ............................................................ 6 added endnote 2 to table 4 ............................................................. 6 changes to figure 2 to figure 4 ....................................................... 7 change s to figure 10 ...................................................................... 12 changes to figure 15, figure 17 to figure 19, figure 37, and figure 39 ...................................................................................... 14 changes to figure 23 to figure 26 captions ................................ 15 change to figure 35 caption ......................................................... 17 added fi gure 46 and figure 47 ..................................................... 20 changes to figure 51 ...................................................................... 21 changes to clock duty cycle considerations section .............. 22 changes to power dissipation and power - down mode section ... 23 changes to figure 61 to figure 63 captions ............................... 25 changes to table 9 endnote .......................................................... 26 changes to digita l outputs and timing section ........................ 27 added table 10 ................................................................................ 27 changes to rbias pin section ...................................................... 28 deleted figure 62 and figure 63 ................................................... 27 changes to figure 67 ...................................................................... 29 changes to hardware interface section ....................................... 30 added figure 68 .............................................................................. 31 changes to table 15 ........................................................................ 31 changes to reading the memory ma p table section ................ 32 change to input signals section ................................................... 36 changes to output signals section ............................................... 36 changes to figure 71 ...................................................................... 36 changes to default operation and jumper selection settings section ........................................... 37 changes to alternative analog input drive configuration sec tion .................................................... 38 changes to figure 74 ...................................................................... 40 changes to table 17 ........................................................................ 48 changes to ordering guide ........................................................... 52 4/06 revision 0: initial version
ad9228 rev. d | page 4 of 56 specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 1. ad9228 - 40 ad9228 - 65 parameter 1 temperature min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full guaranteed guaranteed offset error full 1 8 1 8 mv offset matching full 2 8 2 8 mv gain error full 0.4 1.2 2 3.5 % fs gain matching full 0.3 0.7 0.3 0.7 % fs differential nonlinearity (dnl) full 0.25 0.5 0.3 0.65 lsb integral nonlinearity (inl) full 0.4 1 0.4 1 lsb temperature drift offset error full 2 2 ppm/ c gain error full 17 17 ppm/ c reference voltage (1 v mode) full 21 21 ppm/ c reference output voltage error (v ref = 1 v) full 2 30 2 30 mv l oad regulation at 1.0 ma (v ref = 1 v) full 3 3 mv input resistance full 6 6 k? analog inputs differential input voltage (v ref = 1 v) full 2 2 v p -p common - mode voltage full avdd/2 avdd/2 v differential input capacitance full 7 7 pf analog bandwidth, full power full 315 315 mhz power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd full 155 170 232 245 ma i drvdd full 31 34 34 38 ma total power dissipation (including output drivers) full 335 367 478 510 mw power - down dissipation full 2 5.8 2 5.8 mw standby dissipation 2 full 72 72 mw crosstalk full ?100 ?100 db crosstalk (overrange condition) 3 full ?100 ?100 db 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how thes e t est s were completed. 2 can be controlled via the spi. 3 overr ange condition is specific with 6 db of the full - scale input range.
ad9228 rev. d | page 5 of 56 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 2. ad9 228 - 40 ad9228 - 65 parameter 1 temperature min typ max min typ max unit signal - to - noise ratio (snr) f in = 2.4 mhz full 70.5 70.2 db f in = 19.7 mhz full 68.5 70.2 70.0 db f in = 35 mhz full 70.2 68.5 70.0 db f in = 70 mhz full 70.0 69.5 db signal - to - noise and distortion ratio (sinad) f in = 2.4 mhz full 70.3 70.0 db f in = 19.7 mhz full 68.0 69.8 70.0 db f in = 35 mhz full 69.7 68.0 69.8 db f in = 70 mhz full 69.5 69.0 db effective number of bits (enob) f in = 2.4 mhz full 11.42 11.37 bits f in = 19.7 mhz full 11.1 11.37 11.33 bits f in = 35 mhz full 11.37 11.1 11.33 bits f in = 70 mhz full 11.33 11.25 bits spurious- free dynamic range (sfdr) f in = 2.4 mhz full 85 85 dbc f in = 19.7 mhz full 72 82 85 dbc f in = 35 mhz full 80 73 84 dbc f in = 70 mhz full 80 74 dbc worst harmonic (second or third) f in = 2.4 mhz full ?85 ?85 dbc f in = 19.7 mhz full ?82 ?72 ?85 dbc f in = 35 mhz full ?80 ?84 ?73 dbc f in = 70 mhz full ?80 ?74 dbc worst other (excluding second or third) f in = 2.4 mhz full ?90 ?90 dbc f in = 19.7 mhz full ?90 ?80 ?90 dbc f in = 35 mhz full ?90 ?90 ?79 dbc f in = 70 mhz full ?90 ?88 dbc two - tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 15 mhz, f in2 = 16 mhz 25c 80.8 77.8 dbc f in1 = 70 mhz, f in2 = 71 mhz 25c 75.0 77.0 dbc 1 see the an - 835 application note , understanding high speed adc testing and eva luation , f or definitions and for details on how these t est s were completed.
ad9228 rev. d | page 6 of 56 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 3. ad9228 - 40 ad9228 - 65 parameter 1 temperature min typ max min typ max un it clock inputs (clk+, clk ?) logic compliance cmos/lvds/lvpecl cmos/lvds/lvpecl differential input voltage 2 full 250 250 mv p -p input common - mode voltage full 1.2 1.2 v input resistance (differential) 25c 20 20 k? input capacit ance 25c 1.5 1.5 pf logic inputs (pdwn, sclk/dtp) logic 1 voltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0 0.3 0.3 v input resistance 25c 30 30 k? input capacitance 25c 0.5 0.5 pf logic input (csb) logic 1 vo ltage full 1.2 3.6 1.2 3.6 v logic 0 voltage full 0 0.3 0.3 v input resistance 25c 70 70 k? input capacitance 25c 0.5 0.5 pf logic input (sdio/odm) logic 1 voltage full 1.2 drvdd + 0.3 1.2 drvdd + 0.3 v logic 0 voltage full 0 0.3 0 0.3 v input resistance 25c 30 30 k? input capacitance 25c 2 2 pf logic output (sdio/odm) 3 logic 1 voltage (i oh = 800 a) full 1.79 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 0.05 v digital outputs (d + x , d ? x) , (ansi - 644) logic compliance lvds lvds differential output voltage (v od ) full 247 454 247 454 mv output offset voltage (v os ) full 1.125 1.375 1.125 1.375 v output coding (default) offset binary offset binary digital outputs (d + x , d ? x ), (low power, reduced signal option) logic compliance lvds lvds differential output voltage (v od ) full 150 250 150 250 mv output offset voltage (v os ) full 1.10 1.30 1.10 1.30 v output coding (default) offset binary offset binar y 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these t est s were completed. 2 this is specified for lvds and lvpecl only. 3 this is specified for 13 sdio pins sharing the same connection.
ad9228 rev. d | page 7 of 56 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?0.5 dbfs, unless otherwise noted. table 4. ad9228 - 40 ad9228 - 65 parameter 1 , 2 temp min typ max min typ max unit clock 3 maximum clock rate full 40 65 msps minimum clock rate full 10 10 msps clock pulse width high (t eh ) full 12.5 7.7 ns clock pulse width low (t el ) full 12.5 7.7 ns output parameters 3 propagation delay (t pd ) full 2.0 2.7 3.5 2.0 2.7 3.5 ns rise time (t r ) (20% to 80%) full 300 300 ps fall time (t f ) (20% to 80%) full 300 300 ps fco propagation delay (t fco ) full 2.0 2.7 3.5 2.0 2.7 3.5 ns dco propagation delay (t c pd ) 4 full t fco + (t sample /24) t fco + (t sample /24) ns dco to data delay (t data ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t fr ame ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data to data skew (t data - max ? t data - min ) full 50 150 50 150 ps wake - up time (standby) 25c 6 00 600 ns wake - up time (power - down) 25c 375 375 s pipeline latency full 8 8 clk cycles aperture aperture delay (t a ) 25c 500 500 ps aperture uncertainty (jitter) 25c <1 <1 ps rms out -of- range recovery time 25c 1 2 clk cycles 1 see t he an - 835 application note , understanding high speed adc testing and ev aluation , for definitions and for details on how these tests were completed. 2 measured on standard fr -4 material. 3 can be adjusted via the spi . 4 t sample /24 is based on the number of bits divided by 2 because the dela ys are based on half duty cycles.
ad9228 rev. d | page 8 of 56 timing diagrams dco? dco+ d ? x d + x fco? fco+ vin x clk? clk+ msb n ? 9 d10 n ? 9 d9 n ? 9 d8 n ? 9 d7 n ? 9 d6 n ? 9 d5 n ? 9 d4 n ? 9 d3 n ? 9 d2 n ? 9 d1 n ? 9 d0 n ? 9 d10 n ? 8 msb n ? 8 05727-039 n ? 1 n t da ta t frame t fco t pd t cpd t eh t a t el figure 2 . 12 - bit data serial stream , msb first (default) dc o+ dc o? cl k+ fc o+ fc o? d ? x d + x cl k? vin x msb n ? 9 n ? 1 n d8 n ? 9 d7 n ? 9 d5 n ? 9 t da ta t frame t fco t pd d4 n ? 9 d6 n ? 9 d8 n ? 8 d7 n ? 8 d5 n ? 8 d6 n ? 8 d3 n ? 9 d1 n ? 9 msb n ? 8 d0 n ? 9 d2 n ? 9 t cpd t eh t a t el 05727-040 figure 3 . 10 - bit data serial stream , msb first
ad9228 rev. d | page 9 of 56 dco? dco+ d ? x d + x fco? fco+ vin x clk? clk+ lsb n ? 9 d0 n ? 9 d1 n ? 9 d2 n ? 9 d3 n ? 9 d4 n ? 9 d5 n ? 9 d6 n ? 9 d7 n ? 9 d8 n ? 9 d9 n ? 9 d10 n ? 9 d0 n ? 8 lsb n ? 8 05727-041 n ? 1 t a n t da ta t frame t fco t pd t cpd t eh t el figure 4 . 12 - bit data serial stream, lsb first
ad9228 rev. d | page 10 of 56 absolute maximum rat ings table 5. parameter with respect to rating electrical avdd agnd ?0.3 v to +2.0 v drvdd drgnd ?0.3 v to +2.0 v agnd drgnd ?0.3 v to +0.3 v avdd drvdd ?2.0 v to +2.0 v digital outputs (d + x , d ? x , dco+, dco ?, fco+, fco?) drgnd ?0.3 v to +2.0 v clk+, clk ? agnd ?0.3 v to +3.9 v vin + x , vin ? x agnd ?0.3 v to +2. 0 v sdio/odm agnd ?0.3 v to +2.0 v pdwn, sclk/dtp, csb agnd ?0.3 v to +3.9 v reft, refb, rbias agnd ?0.3 v to +2.0 v vref, sense agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40 c to +85 c maximum junction temperatu re 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal imped ance table 6. air flow velocity (m/sec) ja 1 jb jc unit 0.0 24 c/w 1.0 21 12.6 1.2 c/w 2.5 19 c/w 1 ja for a 4 - layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution
ad9228 rev. d | page 11 of 56 pin configuration and function descripti ons vin + a vin ? a av dd vi n + d vi n ? d dr vdd dr gnd cl k+ cl k? av dd dr vdd dr gnd av dd av dd csb sclk/ dtp sdio/ odm pdwn av dd av dd av dd av dd av dd av dd d + a d ? a d + b d ? b d + c d ? c d + d d ? d dco+ dco? fco+ fco? vin + b vin ? b vin + c vin ? c avdd reft refb vref sense avdd avdd rbias 11 12 10 9 8 7 6 5 4 3 2 1 25 24 26 27 28 29 30 31 32 33 34 35 36 22 21 23 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 05727-003 pin 1 indicator exposed paddle, pin 0 (bottom of package) ad9228 top view notes 1. the exposed pad must be connected to analog ground. figure 5 . 48 - lead lfcsp pin configuration , top view table 7 . pin function descriptions pin no. mnemonic description 0 agnd analog ground (exposed paddle) 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46 avdd 1.8 v analog supply 11, 26 drgnd digital output driver ground 12, 25 drvdd 1.8 v digital output driver supply 3 vin ? d adc d analog input complement 4 vin + d adc d analog input true 7 clk? input clock complement 8 clk+ input clock true 13 d ? d adc d digital output complement 14 d + d adc d digital output true 15 d ? c adc c digital output complement 16 d + c adc c digital output true 17 d ? b adc b digital output complement 18 d + b adc b digital output true 19 d ? a adc a digital output complement 20 d + a adc a digital output true 21 fco ? frame clock output complement 22 fco+ frame clock outpu t true 23 dco ? data clock output complement 24 dco+ data clock output true 28 sclk/dtp serial clock/digital test pattern 29 sdio/odm serial data io /output driver mode 30 csb c hip select b ar 31 pdwn power - down
ad9228 rev. d | page 12 of 56 pin no. mnemonic description 33 vin + a adc a analog input true 34 v in ? a adc a analog input complement 37 vin ? b adc b analog input complement 38 vin + b adc b analog input true 40 rbias external resistor sets the internal adc core bias current 41 sense reference mode selection 42 vref voltage reference input/outpu t 43 refb differential reference (negative) 44 reft differential reference (positive) 47 vin + c adc c analog input true 48 vin ? c adc c analog input complement
ad9228 rev. d | page 13 of 56 equivalent circuits vin x 05727-030 figure 6 . equivalent analog input circu it 10? 10k? 10k? clk? 10? 1.25v 05727-032 clk+ figure 7 . equivalent clock input circuit 05727-035 sdio/odm 350? 30k? figure 8 . equivalent sdio/odm input circuit dr vdd drgnd d? d+ v v 05727 -005 v v figure 9 . equivalent digital output circuit sclk/dtp and pdwn 05727-033 30k? 1k? figure 10 . equivalent sclk/dtp and pdwn input circuit 100? rbias 05727-031 figure 11 . equivalent rbias circuit
ad9228 rev. d | page 14 of 56 csb 05727-034 70k? 1k? a vdd figure 12 . equivalent csb input circuit sense 05727-036 1k? figure 13 . equivalent sense circuit vref 05727-037 6k ? figure 14 . equivalent vref circuit
ad9228 rev. d | page 15 of 56 typical performance characteristics ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 10 12 14 16 18 20 05727-052 amplitude (dbfs) frequency (mhz) ain = ?0.5dbfs snr = 70.51db enob = 1 1.42 bits sfdr = 86.00dbc figure 15 . single - tone 32k fft with f in = 2. 4 mhz, f sample = 40 msps 0 141210 8642 1816 20 amplitude (dbfs) frequency (mhz) 05727-085 ?120 ?100 ?80 ?60 ?40 ?20 0 ain = ?0.5dbfs snr = 70.38db enob = 1 1.40 bits sfdr = 81.13dbc figure 16 . single - tone 32k fft with f in = 35 mhz, f sample = 40 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-053 ain = ?0.5dbfs snr = 70.53db enob = 1 1.42 bits sfdr = 86.04dbc figure 17 . single - tone 32k fft with f in = 2.3 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-054 ain = ?0.5dbfs snr = 69.62db enob = 1 1.27 bits sfdr = 72.48dbc figure 18 . single - tone 32k fft with f in = 70 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-055 ain = ?0.5dbfs snr = 68.74db enob = 1 1.12 bits sfdr = 72.99dbc figure 19 . single - tone 32k fft with f in = 120 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-056 ain = ?0.5dbfs snr = 67.68db enob = 10.95 bits sfdr = 62.23dbc figure 20 . single - tone 32k fft with f in = 170 mhz, f sample = 65 msps
ad9228 rev. d | page 16 of 56 0 5 10 15 20 25 30 frequency (mhz) 05727-057 ain = ?0.5dbfs snr = 67.58db enob = 10.93 bits sfdr = 68.39dbc amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 figure 21 . single - tone 32k fft with f in = 190 mhz, f sample = 65 msps 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-058 ain = ?0.5dbfs snr = 65.56db enob = 10.6 bits sfdr = 62.72dbc ?120 ?100 ?80 ?60 ?40 ?20 0 figure 22 . single - tone 32k fft with f in = 250 mhz, f sample = 65 msps snr/sfdr (db) encode (msps) 05727-059 60 65 70 75 80 85 90 10 15 20 25 30 35 40 2v p-p, sfdr 2v p-p, snr figure 23 . snr/sfdr vs. encode , f in = 10.3 mhz, f sample = 40 msps snr/sfdr (db) encode (msps) 05727-061 68 10 15 20 25 30 35 40 2v p-p, sfdr 2v p-p, snr 70 72 74 76 78 80 82 84 figure 24 . snr/sfdr vs. encode , f in = 35 mhz, f sample = 40 msps snr/sfdr (db) encode (msps) 05727-062 60 65 70 75 80 85 90 10 20 30 40 50 60 2v p-p, sfdr 2v p-p, snr figure 25 . snr/sfdr vs. encode , f in = 10.3 mhz, f sample = 65 msps snr/sfdr (db) encode (msps) 05727-064 68 72 70 74 76 78 82 80 84 10 20 30 40 50 60 2v p-p, sfdr 2v p-p, snr figure 26 . snr/sfdr vs. encode , f in = 35 mhz, f sample = 65 msps
ad9228 rev. d | page 17 of 56 snr/sfdr (db) 05727-065 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?1 0 0 f in = 10 .3mhz f sample = 40msps 2v p-p, sfdr 2v p-p, snr 80 db refere nc e ana l og i nput level (dbfs) figure 27 . snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 40 msps snr/sfdr (db) ana l og i nput level (dbfs) 05727-066 0 10 20 30 40 50 60 70 80 90 100 ?6 0 ?50 ?40 ?3 0 ?20 ?1 0 0 f in = 35 mhz f sample = 40msps 2v p-p, sfdr 2v p-p , snr 80 db refere nc e figure 28 . snr/sfdr vs. analog input level, f in = 35 mhz, f sample = 40 msps snr/sfdr (db) 05727-068 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?1 0 0 f in = 10 .3mhz f sample = 65msps 2v p-p, sfdr 2v p-p, snr 80 db refere nc e ana l og i nput l evel (dbfs) figure 29 . snr/sfdr vs. analog input level, f in = 10.3 mhz, f sample = 65 msps snr/sfdr (db) 05727-070 0 10 20 30 40 50 60 70 80 90 100 ?60 ?50 ?40 ?30 ?20 ?1 0 0 f in = 35 mhz f sample = 65msps 2v p-p, sfdr 2v p-p, snr ana l og i nput level (dbfs) 80 db refere nc e figure 30 . snr/sfdr vs. analog input level, f in = 35 mhz, f sample = 65 msps ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 10 12 14 16 18 20 05727-049 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 80.75dbc imd2 = 85.53dbc imd3 = 80.83dbc figure 31 . two - tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, f sample = 40 msps ?40 ?60 ?80 ?100 ?20 0 ?120 0 2 4 6 8 10 12 14 16 18 20 05727-050 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 74.76dbc imd2 = 81.03dbc imd3 = 75.00dbc figure 32 . two - tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, f sample = 40 msps
ad9228 rev. d | page 18 of 56 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 05727-048 amplitude (dbfs) frequency (mhz) ain1 and ain2 = ?7dbfs sfdr = 78.15dbc imd2 = 77.84dbc imd3 = 88.94dbc figure 33 . two - tone 32k fft with f in1 = 15 mhz and f in2 = 16 mhz, f sample = 65 msps 0 ?40 ?60 ?80 ?100 ?20 ?120 0 5 10 15 20 25 30 amplitude (dbfs) frequency (mhz) 05727-051 ain1 and ain2 = ?7dbfs sfdr = 76.75dbc imd2 = 77.56dbc imd3 = 77.01dbc figure 34 . two - tone 32k fft with f in1 = 70 mhz and f in2 = 71 mhz, f sample = 65 msps snr/sfdr (db) 05727-071 50 55 60 65 70 75 80 85 90 1 10 100 1000 frequency (mhz) 2v p-p, sfdr 2v p-p, snr figure 35 . snr/sfdr vs. frequency , f sample = 65 msps sinad/sfdr (db) temperature (c) 05727-072 ?40 ?20 80 60 40 20 0 60 65 70 75 80 85 90 2v p-p, sinad 2v p-p, sfdr figure 36 . sinad/sfdr vs. temperature, f in = 10.3 mhz, f sampl e = 65 msps 1.0 ?1.0 0 4000 3500 3000 2500 2000 1500 1000 500 code inl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 05727-073 figure 37 . inl, f in = 2.4 mhz, f sample = 65 msps ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) code 05727-074 0 500 1000 1500 2000 2500 3000 3500 4000 figure 38 . dnl, f in = 2.4 mhz, f sample = 65 msps
ad9228 rev. d | page 19 of 56 ?45.0 ?46.0 ?45.5 ?46.5 ?47.0 ?47.5 ?48.0 10 15 20 25 35 45 30 40 50 cmrr (db) frequency (mhz) 05727-075 figure 39 . cmrr vs. frequency, f sample = 65 msps number of hits (millions) 05727-086 0.2 0.4 0.6 0.8 1.0 1.2 0 n ? 3 n ? 2 n + 3 n + 2 n + 1 n n ? 1 code 0.26 lsb rms figure 40 . input - referred noise histogram, f sample = 65 msps amplitude (dbfs) 05727-076 ?120 0 ?20 ?40 ?60 ?80 ?100 0 5 10 15 20 30 25 frequency (mhz) npr = 60.83db notch = 18.0mhz notch width = 3.0mhz figure 41 . noise power ratio (npr), f sample = 65 msps fundamental level (db) 05727-077 ?10 0 ?3 ?2 ?1 ?4 ?5 ?6 ?7 ?8 ?9 0 50 100 150 200 250 300 350 400 450 500 frequency (mhz) ?3db cutoff = 315mhz figure 42 . full - power bandwidth vs. frequency, f sample = 65 msps
ad9228 rev. d | page 20 of 56 theory of operation the ad9228 architecture consists of a pipelined adc divided into three sections: a 4 - bit first stage followed by eight 1.5 - bit stages and a final 3 - bit flash. each stage provides sufficient overlap to correct for flash erro rs in th e preceding stage . the quantized outputs from each stage are combined into a final 12 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier ( for example, a multiplying digital - to - analog converter (mdac) ). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction o f flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects error s , and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clock s. analog input conside r ations the analog input to the ad9228 is a differential switched - capacitor circuit designed for processing differential input signals. th is circuit can support a wide common - mode range while maintain ing exce l lent performance. by using a n input common - mode voltage of midsupply , users can minimize signal - dependent e r rors and achieve optimum performance. s s h c par c sample c sample c par vi n ? x h s s h vi n + x h 05727-006 figure 43 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sa m ple mode and hold m ode (see figure 43 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each inp ut can help reduce the peak transient current injected from the output stage of the driving source. in addition, low - q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and theref ore achieve the maximum bandwidth of the adc. such use of low - q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provi de a matching passive network. this ultimately creates a low -pass filter at the i n put to limit unwanted broadband noise. see the an - 742 application note , the an - 827 ap plication note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in gene ral, the precise values depend on the appl i cation. the analog inputs of the ad9228 are not internally dc - biased. therefore, i n ac - coupled applications, the user must provide this bias exte r nally. setting the device so that v cm = avdd /2 is recom mended for o ptimum perfor m ance, but the device can function over a wider range with reaso n able performance, as shown in figure 44 to figure 47 .
ad9228 rev. d | page 21 of 56 snr/sfdr (db) ana l og i nput common-mode vo lt ag e (v) 05727-078 50 55 60 65 70 75 80 85 90 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 sfdr (dbc) snr (db) figure 44 . snr/sfdr vs. common - mode volt age, f in = 2.4 mhz, f sample = 65 msps snr/sfdr (db) ana l og i nput common-mode vo lt age (v) 05727-079 50 55 60 65 70 75 80 85 90 0. 2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 sfdr (dbc) snr (db) figure 45 . snr/sfdr vs. common - mode voltage, f in = 30 mhz, f sample = 65 msps 90 50 0.2 1.6 analog input common-mode voltage (v) snr/sfdr (db) 85 80 75 70 65 60 55 0.4 0.6 0.8 1.0 1.2 1.4 snr (db) sfdr (dbc) 05727-100 figure 46 . snr/sfdr vs. common - mode voltage, f in = 2.4 mhz, f sample = 40 msps 90 50 0.2 1.6 analog input common-mode voltage (v) snr/sfdr (db) 85 80 75 70 65 60 55 0.4 0.6 0.8 1.0 1.2 1.4 snr (db) sfdr (dbc) 05727-101 figure 47 . snr/sfdr vs. common - mode voltage, f in = 30 mhz, f sample = 40 msps
ad9228 rev. d | page 22 of 56 for best dynamic performance, the source impedances driving vin + x and vin ? x should be matched such that common - mode settling errors are symmetric al. these errors are reduced by the common - mode rejection of the adc. an internal reference buffer creates the positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common - mode of the refere nce buffer is set to midsupply, and the reft and refb voltages and span are defined as reft = 1/2 ( avdd + vref ) refb = 1/2 ( avdd ? vref ) span = 2 ( reft ? refb ) = 2 vref it can be seen from these equations that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9228, the largest input span available is 2 v p - p. differential input configurations there are several ways to drive the ad9228 either actively or pas sively ; however , optimum performance is achieved by driving the analog input differentially. for example , using the ad8332 differential driver to drive the ad9228 pr o vides excellent p erfor - mance and a flexible interface to the adc (see figure 51 ) for baseband applications. this configuration is common ly used for medical ultrasound systems. for applications where snr is a key p arameter, differential transfo r mer coupling is the recommended input configuration (see figure 48 and figure 49) , because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9228. regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. 05727-008 2v p-p r r *c diff c *c diff is optional 49.9 0.1f 1k 1k a gnd a vdd adt1-1wt 1:1 z ratio vin ? x adc ad9228 vin + x c figure 48 . differential transformer - coupled configuration for baseband application s adc ad9228 05727-047 2v p-p 2.2pf 1k ? 0.1f 1k 1k a vdd adt1-1wt 1:1 z ratio 16nh 16nh 0.1f 16nh 33 ? 33 ? 499 ? 65 ? vin + x vin ? x figure 49 . differential transformer - coupled configuration for if applications single - ended input configuration a single - ended input may provide adequate performance in cost - sensitive applications. in this configuration, sfdr a nd distortion performance degrade due to the large input common - mode swing. if the application requires a single - ended input configuration, ensure that the source i m pedances on each input are well matched in order to achieve the best possible performance. a full - scale input of 2 v p - p can be applied to the adcs vin + x pin while the vin ? x pin is terminated. figure 50 details a typical single - ended input configuration. 05727-009 2v p-p r r 49.9 0.1f 0.1f a vdd 1k 25 1k 1k a vdd vin ? x adc ad9228 vin + x *c diff c *c diff is optional c figure 50 . single - ended input configuration ad8332 1k 187 187 0.1f 0.1f 0.1f 1v p-p 0.1f ln a 120nh vga voh vip inh 22pf lmd vin lo p lon vol 18nf 274 vin ? x adc ad9228 vin + x 05727-007 lpf + 68pf 33 33 avdd avdd 680nh 680nh 10k 10k 10k 10k figure 51 . differential input configuration using the ad8332 with two- pole , 16 mhz low - pass filter
ad9228 rev. d | page 23 of 56 clock input considerations for optimum performance, the ad9228 sample clock inputs (clk+ and clk ?) should be clocked with a d ifferential signal. this signal is typically ac - coupled to the clk+ and clk ? pins via a transformer or capacitors. these pins are biased i n ternally and require no add i tional bias ing . figure 52 shows a preferred method for cloc king the ad9228. the low jitter clock source is converted from a single - ended signal to a differential signal using an rf transformer. the back - to - back schottky diodes across the secondary transformer limit clock excursions into the ad9228 to approximately 0.8 v p - p diffe r ential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9228 , and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1 f s chottk y diodes: hsm2812 clk+ 50? 100? clk? clk+ adc ad9228 mini-circuits ? adt1-1w t , 1:1z xfmr 05727-024 figure 52 . transformer - coupled differential clock a nother option is to ac - couple a differential pecl signal to the sample clock input pins as shown in figure 53 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers o f fers excellent jitter performance. ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515 10 0? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 05727-025 50 ?* 50 ?* clk clk *50 ? resis t ors are option al clk? clk+ adc ad9228 pecl driver clk+ clk? figure 53 . differential pecl sample clock ad9510/ad95 1 1/ ad9512/ad 9513/ ad9514/ad9515 05727-026 10 0 ? 0.1f 0.1f 0.1f 0.1f 50?* 50?* clk clk *50 ? resis t ors are option al clk? clk+ adc ad9228 l vds driver clk+ clk? figure 54 . differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single - ended cmos signal. in such applic ations, clk+ should be driven directly from a cmos gate, and the clk ? pin should be bypassed to ground with a 0.1 f c a pacitor in parallel with a 39 k ? resistor (see figure 55 ). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages of up to 3.3 v and therefore offers several sele c tion s for the drive logic voltage . ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515 05727-027 0.1f 0.1f 0.1f 39 k? 50 ?* opti on al 100 ? 0.1f clk clk *50 ? resis t or is option al clk? clk+ adc ad9228 cmos driver clk+ figure 55 . single - ended 1.8 v cmos sample clock ad9510/ad95 1 1/ ad9512/ad9513/ ad9514/ad9515 05727-028 0.1f 0.1f 0.1f 50 ?* clk clk *50 ? resis t or is option al 0.1f clk? clk+ adc ad9228 optiona l 100? cmos driver clk+ figure 56 . single - ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sens i tive to the clock duty cycle. commonly, a 5% tolera nce is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9228 contains a duty cycle stab i lizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nom i nal 50% duty cycle. this allows a wi de range of clock input duty cycles without affecting the perfor m ance of the ad9228. when the dcs is on, noise and distortion perfor - mance are nearly flat for a wide range of duty c y cles. however, some applications may require the dcs function to be off. i f so, keep in mind that the dynamic range performance can be affected when operated in this mode. see the memory map section for more details on using this feature. jitter in the rising edge of the input is an important concern , and it is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz nominal. the loop has a time constant associated with it that must be considered in applications where the clock rate can change dynamically. this requires a wait time of 1.5 s to 5 s after a dynamic clock frequency increase (or decrease) before the dcs loop is relocked to the input signal. during the period that the loop is not locked, the dcs loop is bypassed an d the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac perfo rmance.
ad9228 rev. d | page 24 of 56 clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input fr e quency ( f a ) due only to aperture jitter ( t j ) can be calc u lated by snr degradation = 20 log 10 ( 1/2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter . if unde r sampling applications are particularly sensitive to jitter (see figure 57 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9228. power supplies for clock drivers should be separated from the adc output driver s upplies to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators are the best clock sources. if the clock is generated from another type of source (by gating, dividing, or an other met h od ), it should be retimed by the original clock during the last step. refer to the an - 501 application note and to the an - 756 application note for more in - depth information about jitter performa nce as it relates to adcs. 1 10 100 1000 05727-038 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps anal og i npu t f requ ency (mhz) 10 bits rms clock jitter requirement snr (db) figure 57 . ideal snr vs. input frequency and jitter power dissipation and power - down mode as shown in figure 58 and figure 59 , the power dissip ated by the ad9228 is proportional to its sample rate. the digital power dissipation does not vary significantly be cause it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 10 20 15 30 35 25 40 current (ma) encode (msps) 05727-089 180 220 200 240 300 340 320 360 260 280 0 20 40 100 140 120 180 160 60 80 drvdd current total power avdd current power (mw) figure 58 . supply current vs. f sample for f in = 10.3 mhz, f sample = 40 msps 10 20 30 40 50 60 current (ma) power (mw) encode (msps) 05727-081 0 50 100 150 200 250 300 340 320 360 380 400 420 440 460 480 drvdd current total power avdd current figure 59 . supply current vs. f sample for f in = 10.3 mhz, f sample = 65 msps
ad9228 rev. d | page 25 of 56 by asserting the pdwn pin high, the ad9228 is placed in to power - down mode. in this state, th e adc typically dissipates 3 mw. during power - down, the lvds output drivers are placed in to a high impedance state. if any of the spi features are changed before the power - down feature is enabled , the chip continue s to function after pdwn is pulled low wit hout requiring a reset . the ad9228 returns to normal oper a ting mode when the pdwn pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. in power - down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering power - down mode and must be recharged when r e turning to normal operation. as a result, the wake - up time is related to the time spent in the power - down mode : shorter cycles result in proportionally shorter wake - up times. with the recommended 0.1 f and 2.2 f decoupling capacitors on reft and refb, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 s is required to restore full operation. there are several other power - down options available when using the spi. the user can individually power down each channel or put the entire device into standby mode. th e latter option allows the user to keep the interna l pll powered when fast wake - up times (~600 ns) are required. see the memory map section for more details on using these features. digital outputs and timing the ad9228 differential outputs conform to the ansi - 644 lvds standar d on default power - up. this can be changed to a low power, reduced signal option ( similar to the ieee 1596.3 standard ) via the sdio/odm pin or spi. th e lvds standard can further reduce the overall power dissipation of the device by approximately 15 mw. see the sdio/odm pin section or table 16 in the memory map section for more information. the lvds driver current is derived on - chip and sets t he output current at each o utput equal to a nominal 3.5 ma. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the ad9228 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas f or superior switching performance in noisy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as clos e to the receiver as possible. if there is n o far - end receiver termination or there is poor differential trace routing , timing errors may resul t. to avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. an example of the fco and data st ream with proper trace length and position is shown in figure 60 . 05727-045 ch1 200mv/div = dco ch2 200mv/div = data ch3 500mv/div = fco 2.5ns/div figure 60 . ad922 8- 65, lvds output timing example in ansi - 644 mode (default) an example of the lvds output using the ansi - 644 standar d (default) data eye and a time interval error (tie) jitter histogram with trace lengths less than 24 inches on standard fr - 4 material is shown in figure 61. figure 62 shows an example of trace le ngths exceed ing 24 inches on standard fr - 4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the user s resp on - sibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to fu rther increase the internal ter mination (increasing the current) of all four outputs in order to drive longer trace lengths (see figure 63 ). even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is used. in addition, notice in figure 63 that the histogram is improved compared with that shown in figure 62 . see the memory map section for more details.
ad9228 rev. d | page 26 of 56 05727-043 100 50 0 ?100ps 0ps 100ps tie jitter histogram (hits) 500 ?500 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 10000/15600 figure 61 . data eye for lvds outputs in ansi- 644 mode with trace lengths less than 24 inches on standard fr - 4, external 100 ? far termination only 05727-044 200 ?200 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 9600/15600 100 50 0 ?150ps ?100ps ?50ps 0ps 50ps 100ps 150ps tie jitter histogram (hits) figure 62 . data eye for lvds outputs in ansi - 644 mode with trace lengths greater than 24 inches on standard fr - 4, external 100 ? far termination only 100 50 0 ?150ps ?100ps ?50ps 0ps 50ps 100ps 150ps tie jitter histogram (hits) 05727-042 200 400 ?200 ?400 0 ?1ns ?0.5ns 0ns 0.5ns 1ns eye diagram voltage (v) eye: all bits uls: 9599/15599 figure 63 . data eye for lvds outputs in ansi- 644 mode with 100 ? internal termination on and trace lengths greater than 24 inches on standard fr -4, external 100 ? far termination only the format of the output data is offset binary by default. an example of the output coding format can be found in table 8 . t o change the output data format to twos complement, see the memory map section. table 8 . digital output coding code (vin + x ) ? (vin ? x ), input span = 2 v p - p (v) digital output offset binary (d11 ... d0) 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000488 0111 1111 1111 0 ?1.00 0000 0000 0000 data from each adc is serialized and provided on a separate c hannel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 mbps (12 bits 65 msps = 780 mbps). the lowest typical conversion rate is 10 msps. however, if lower sample rates are required for a specif ic application, the pll can be set up via the spi to allow encode rates as low as 5 msps. see the memory map section for details on enabling this feature.
ad9228 rev. d | page 27 of 56 two output clocks are provided to assist in capturing data from the ad9 228. the dco is used to clock the output data and is equal to six times the sampl e clock (clk) rate. data is clocked out of the ad9228 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the fco i s used to signal the start of a new output byte and is equal to the sampl e clock rate. see the timing diagram shown in figure 2 for more information. table 9 . flex ible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 (8 - bit) 10 0000 0000 (10 - bit ) 1000 0000 0000 (12 - bit ) 10 0000 0000 0000 (14 - bit ) same yes 0010 +full - scale short 1111 1111 (8 - bit ) 11 1111 1111 (10 - bit ) 1111 1111 1111 (12 - bit ) 11 1111 1111 1111 (14 - bit ) same yes 0011 ?full - scale short 0000 0000 (8 - bit ) 00 0000 0000 (10 - bit ) 0000 0000 0000 (12 - bit ) 00 0000 0000 0000 (14 - bit ) same yes 0100 checkerboard 1010 1010 (8 - bit ) 10 1010 1010 (10 - bit ) 1010 1010 1010 (12 - bit) 10 1010 1010 1010 (14 - bit ) 0101 0101 (8 - bit ) 01 0101 01 01 (10- bit ) 0101 0101 0101 (12 - bit ) 01 0101 0101 0101 (14 - bit ) no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one - /zero - word toggle 1111 1111 (8 - bit ) 11 1111 1111 (10 - bit ) 1111 1111 11 11 (12- bit) 11 1111 1111 1111 (14 - bit ) 0000 0000 (8 - bit ) 00 0000 0000 (10 - bit ) 0000 0000 0000 (12 - bit ) 00 0000 0000 0000 (14 - bit ) no 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1-/0 - bit toggle 10 10 1010 (8- bit ) 1 0 1010 1010 (10- bit ) 1010 1010 1010 (12 - bit ) 10 1010 1010 1010 (14 - bit ) n/a no 1010 1 sync 0000 1111 (8 - bit ) 00 0001 1111 (10 - bit ) 0000 0011 1111 (12 - bit ) 00 0000 0111 1111 (14 - bit ) n/a no 1011 one bit high 1000 0000 (8 - bit) 10 0000 0000 (10 - bit ) 1000 0 000 0000 (12- bit ) 10 0000 0000 0000 (14 - bit ) n/a no 1100 mixed frequency 1010 0011 (8 - bit ) 10 0110 0011 (10 - bit ) 1010 0011 0011 (12 - bit ) 10 1000 0110 0111 (14 - bit ) n/a no 1 all test mode options except pn sequence short and pn sequence long can support 8 - to 14 - bit word lengths in order to verify data capture to the receiver.
ad9228 rev. d | page 28 of 56 when the spi is used , the dco phase can be adjusted in 60 increments relative t o the data edge. this enables the user to refine system timing margins if required. the default dco + and dco ? timing, as shown in figure 2 , is 90 relative to the output data edge. an 8 - , 10 -, or 14 - bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower and higher resolution systems. when changing the resolution to an 8 - or 10 - bit serial stream, the data stream is shortened. see figure 3 for the 10 - bit example. however, when using the 14 - bit option, the data stream stuffs two 0s at the end of the 14 - bit serial data. when the spi is used , all of the data outputs can also be inverted from their nominal state. this is not to be confused w ith inverting the serial stream to an lsb - first mode. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. however, this can be inverted so that the lsb is first in the data output serial st ream (see figure 4 ). there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 9 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. n ote that some patterns do not adhere to the data format sele ct opt ion. in addition, custom user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. all test mode options except pn sequence short and pn sequence long can support 8 - to 14 - bit word lengths in order to verify data capt ure to the receiver. the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0.150 (05/96) standard . the only difference is that the starting value must be a specific value instead of all 1s (see table 10 for the initial values). the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the only differences are that the starting value must be a specific value instead of all 1s (see table 10 for the initial values) and the ad92 28 inverts the bit stream with relation to the itu standard . table 10. pn sequence sequence initial value first three output samples (msb fir st) pn sequence short 0x0 df 0xdf9, 0x353, 0x301 pn sequence long 0x29b80a 0x591, 0xfd7, 0x0a3 c onsult the memory map section for information on how to change these additional digital output timing features through the spi. sdio/odm pin the sdio/odm pin is for use in applications that do not require spi mode operation. this pin can enable a low power, reduced signal option ( similar to the ieee 1596.3 reduced range link output standard ) if it and the csb pin are tied to avdd during device power - up. th is option should only be used when the digital output trace lengths are less than 2 inches from the lvds receiver. when this option is used, t he fco, dco, and outputs function normally , but the lvds signal swing of all channels is reduced from 350 mv p - p t o 200 mv p -p, al lowing the user to further reduce the power on the drvdd supply. for applications where this pin is not used, it should be tied low. in this case, the device pin can be left open, and the 30 k ? internal pull - down resistor pulls this pin low. this pin is only 1.8 v tolerant. if applications require this pin to be driven from a 3.3 v logic level, in sert a 1 k ? resistor in series with this pin to limit the current. table 11 . output driver mode pin settings selected odm odm voltage resulting output standard resulting fco and dco normal operation 10 k ? to agnd ansi - 644 (default ) ansi - 644 (default) odm avdd low power, reduced signal option low power, reduced signal option
ad9228 rev. d | page 29 of 56 sclk/dtp pin the sclk/dtp pin is for use in applications that do not require spi mode operation. this pin can enable a single digital test pattern if it an d the csb pin are held high during device power - up. when sclk/dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000. the fco and dco function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignment adjustments among the fco, dco, and output data. for normal operation, this pin should be tied to agnd through a 10 k ? resistor. this pin is both 1.8 v and 3.3 v tolerant. table 12 . d igital test pattern pin settings selected dtp dtp voltage resulting d + x and d ? x resulting fco and dco normal operation 10 k ? to agnd normal operation normal operation dtp avdd 1000 0000 0000 normal operation additional and custom test patterns ca n also be observed when commanded from the spi port. consult the memory map section for information about the options available . csb pin the csb pin should be tied to avdd for applications that do not require spi mode operatio n. by tying csb high, all sclk and sdio information is ignored. this pin is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor (nominally equal to 10.0 k ?) to ground at the rbias pin. the resistor current is derived on - chip and sets t he avdd current of the adc to a nominal 232 ma at 65 msps. therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. voltage reference a stable , accurate 0.5 v voltage reference is built into the ad9228. it is gained up internally by a factor of 2 , setting v ref to 1.0 v, which results in a full - scale differential input span of 2 v p - p. the v ref is set internally by default; however, the vref pin can be driven externally with a 1.0 v reference to improve accuracy. when applying the decoupling capacitors to the vref, reft, and refb pins, use ceramic low esr capacitors. these capa citors should be close to the adc pins and on the same layer of the pcb as the ad9228. the recommended capacitor values and configurations for the ad9228 reference pin are shown in figure 64 . table 13 . reference settings selected mode sense volt age resulting vref (v) resulting differential span (v p - p) external reference avdd n/a 2 external reference internal, 2 v p - p fsr agnd to 0.2 v 1.0 2.0
ad9228 rev. d | page 30 of 56 internal reference operation a comparator within the ad9228 detects the potential at the sens e pin and configures the reference. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 64 ), setting vref to 1 v. the re ft and refb pins establish the input span of the adc core from the reference configuration. the analog input full - scale range of the adc equals twice the voltage of the reference pin for either an internal or an external reference configuration. if the reference of the ad9228 is used to drive multiple c onverters to improve gain matching, the loading of the refe r- ence by the other converters must be considered. figure 66 depicts how the internal reference voltage is affected by loa d ing. 1f 0.1f vref sense 0.5v reft 0.1f 0.1f 2.2f 0.1f refb select logic adc core + 05727-010 vin ? x vin + x figure 64 . in ternal reference configuration 1f 0.1f vref sense a vdd 0.5v reft 0.1f 0.1f 2.2f 0.1f refb select logic adc core + 05727-046 vin ? x vin + x figure 65 . external reference operation external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift characteris tics. figure 67 shows the typical drift characteri s tics of the internal reference in 1 v mode. when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. the external refe rence is loaded with an equivalent 6 k ? load. an internal reference buffer generates the positive and negative full - scale references, reft and refb, for the adc core. therefore, the external refe r ence must be limited to a nominal 1.0 v. 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 v ref error (%) current load (ma) 05727-083 ?30 ?5 ?10 ?15 ?20 ?25 5 0 figure 66 . v ref accuracy vs. load 0.02 ?0.18 ?40 80 60 40 20 0 ?20 temperat u re (c) v ref error (%) 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 ?0.12 ?0.14 ?0.16 05727-084 figure 67 . typical v ref drift
ad9228 rev. d | page 31 of 56 serial port interface (spi) the ad9228 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the adc. this may provide the user with add itional flexibility and customization , depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, as doc umented in the memory map section. detailed operational information can be found in the an - 877 application note , interfacing to high speed adcs via spi . there are three pins that define the spi : sclk, sdio, and csb (see table 14) . the sclk pin is used to synchronize the read and write data presented to the adc. the sdio pin is a dual - purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb pin is an active low control that enables or disables the read and write cycles. table 14 . serial port pins pin function sclk serial clock. the serial shift clock in put . sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual - purpose pin. the typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing sequence. during an instruction phase, a 16 - bit instruction is transmitted followed by one or more data bytes, w hich is determined by bit field w0 and bit field w1. an example of the serial timing and its definitions can be found in figure 69 and table 15. during normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to obtain instructions. normally, csb remains low until the communication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing old er microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until csb is taken high to end the communication cycle. this allows complete memory transfers without requiring additional in struc - tions. regardless of the mode, if csb is taken high in the middle of a byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port configur ation influences how the ad9228 operate s . for applications that do not require a control port, the csb line can be tied and held high. this places the remainder of the spi pins in to their secondary mode s, as defined in the sdio/odm pin and sclk/dtp pin section s . csb can also be tied low to enable 2 - wire mode. when csb is tied low, sclk and sdio are the only pins required for communication. although the device is synchronized during power - up, the user should ensure that the serial port r emains synchronized with the csb line when using this mode . when operating in 2 - wire mode, it is recommended to use a 1 - , 2 -, or 3 - byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word len gth, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change from an input to an output at the appropriate point in the serial frame. data can be sent in msb - or lsb - first mode. msb - first mode is the default at power - up and can be changed by adjusting the configuration register. fo r more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 14 compose the physical interface between the users programming device and the serial port of the ad9228. the sclk and csb pins function as inputs when using the spi . the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. if multiple sdio pins share a common connection, care should be taken to ensure that proper v oh levels are met. assuming the same load for each ad9228 , figure 68 shows the number of sdio pins that can be connected t ogether and the resulting v oh level. this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers, providing the user with an alternative method, other than a full spi controller, to program the adc (see the an - 812 application note ).
ad9228 rev. d | page 32 of 56 05727-102 number of sdio pins connected together v oh (v) 1.715 1.720 1.725 1.730 1.735 1.740 1.745 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 0 3020 10 40 50 60 70 80 90 100 figure 68 . sdio pin loading if the user chooses not to use the spi, these dual - function pins serve their secondary functions when the csb is strapped to avdd during dev ice power - up. see the theory of operation section for details on which pin - strappable functions are supported on the spi pins. for users who wish to operate the adc without using the spi , remove any connections from the csb, sclk/dtp, and sdio/odm pins. by disconnecting these pins from the control bus, the adc can function in its most basic operation. each of these pins has an internal termination that float s to its respective level. don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 05727-012 figure 69 . s erial timing details table 15 . serial timing definitions parameter timing ( m inimum, ns) description t ds 5 set up time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 set up time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 10 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 69 ) t dis_sdio 10 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (no t shown in figure 69 )
ad9228 rev. d | page 33 of 56 memory map reading the memory m ap table each row in the memory map register table ( table 16) has eight address locations. the memory map is divided into three sections: the chi p configur ation register map (address 0x00 to address 0x02), the device index and transfer register map (address 0x05 and address 0xff), and the adc functions register map (address 0x08 to address 0x2 2 ). the left most column of the memory map indicates the register address number, and the defa ult value is shown in the second right most column. the (msb) bit 7 column is the start of the default hexa decimal value given. for example, address 0x09, the clock register , has a default value of 0x01, meaning that bi t 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 6 of this address followed by a 0x01 in register 0xff (transfer bit) , the duty cycle stabilizer turns off. it is important to follow each writing sequence with a transfer bit to update the spi registers. for more information on this and other functions, consult the an- 877 application note , interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power - up. default values when the ad9228 c om es out of a reset, critical registers are preloaded with default values. these values are indicated in table 16 , where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit i s set to logic 0 or writing logic 0 for the bit.
ad9228 rev. d | page 34 of 56 table 16 . memory map register addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments chip configu ration registers 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 the nibbles should be mirrored so that lsb - or msb - first mode i s set cor - rectly regardless of shift mode. 01 chip_id 8- bit chip id bits [ 7:0 ] (ad9228 = 0x02), (default) 0x02 default is unique chip id, different for each device. this is a read - only register. 02 chip_grade x child id [ 6:4 ] (identify device variants of chip id) 000 = 65 msps 001 = 40 msps x x x x read only child id used to differentiate graded devices. device index and transfer registers 05 device_index_a x x clock channel dco 1 = on 0 = off (default) clock channel fco 1 = on 0 = off (default) data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on- chip device receives the next write command. ff device_up date x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes x x x x x internal power - down mode 000 = chip run (default) 001 = full power - down 010 = standb y 011 = reset 0x00 determines various generic modes of chip operation. 09 clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off. 0d test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test mode see table 9 in the digital outputs and timing section 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one - /zero - word toggle 1000 = user input 1001 = 1-/0- bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode ) 0x00 when this reg - ister is set, the test data is placed on the output pins in place of normal data.
ad9228 rev. d | page 35 of 56 addr. (hex) register name (msb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (lsb) bit 0 default value (hex) default notes/ comments 14 output_mode x 0 = lvds ansi - 644 (def ault) 1 = lvds low power (ieee 1596.3 similar) x x x output invert 1 = on 0 = off (default) 00 = offset binary (default) 01 = twos complement 0x00 configures the outputs and the format of the data. 15 output_adjust x x output driver termination 00 = no ne (default) 01 = 200 ? 10 = 100 ? 11 = 100 ? x x x x 0x00 determines lvds or other output properties. primarily func - tions to set the lvds span and common-mode levels in place of an external resistor. 16 output_phase x x x x 0011 = output clock phase a djust (0000 through 1010) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge (default) 0101 = 300 relative to data edge 0110 = 360 relative to data edge 1000 = 480 relativ e to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge 0x03 on devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user -defined pattern, 1 lsb. 1a user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user -defined pattern, 1 msb. 1b user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user -defined pa ttern, 2 lsb. 1c user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user -defined pattern, 2 msb. 21 serial_control lsb first 1 = on 0 = off (default) x x x <10 msps, low encode rate mode 1 = on 0 = off (default) 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 serial stream control. default causes msb first and the native bit stream (global). 22 serial_ch_stat x x x x x x channel output reset 1 = on 0 = off (default) channel power - down 1 = on 0 = off (default) 0x00 used to power down individual sections of a converter (local).
ad9228 rev. d | page 36 of 56 power and ground recommendations when connecting power to the ad9228, it is recommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (d rvdd). if only one supply is available, it should be routed to the avdd first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user can employ several different decoupling capacitor s to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts , with minimal trace length s. a single pc board ground plane should be sufficient when using the ad9228. with proper d ecoupling and smart parti - tioning of the pc boards analog, digital, and clock sections, optimum performance can be easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc be co nnected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9228. an exposed continuous copper plane on the pcb should mate to the ad9228 exposed paddle, pin 0. the copper plane should have several vias to achieve the lo west possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder - filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlayi ng a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process , whereas u sing one continuous plane with no partitions on ly guarantees one tie point . see figure 70 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead fr ame chi p scale package (lfcsp) . silkscreen p artition pin 1 indic at or 05727 -013 figure 70 . typical pcb layout
ad9228 rev. d | page 37 of 56 evaluation board the ad9228 evaluation board provides all of the support cir - cuitry required to operate the adc in its various modes and configurations. the converter can be driven differentially using a transformer (default) or an ad8332 driver. the adc can also be driven in a single - ended fashion. separate power pins are provided to isolate the dut from the drive circuitry of the ad8332 . each input configuration can be selected by changing the connection of various jumpers (see figure 73 to figure 77 ). figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the ad9228. it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noi se performance. see figure 73 to figure 81 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level. power sup plies this evaluation board has a wall - mountable switching power supply that provides a 6 v, 2 a maximum output. c onnect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the other end of the supply is a 2.1 mm inner diameter jack that connects to the pcb at p503. once on the pc board, the 6 v supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the evaluati on board in a nondefault condition, l504 to l507 can be removed to disconnect the switching power supply. this enables the user to bias each section of the board individually. use p501 to connect a different supply for each section. at least one 1.8 v supp ly is needed for avdd_dut and drvdd_dut; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 a . to operate the evaluation board using the vga option, a separate 5.0 v analog supply (avdd_5 v) is needed. to operate the evaluation board using the spi and alternate clock options, a separate 3.3 v analog supply (avdd_3.3 v) is needed in addition to the other supplies. input signals when connecting the clock and analog sourc e s to the evaluation board , use clean signal generators with low phase noise, such as rohde & schwarz sm hu or hp8644b signal generators or the equivalent , as well as a 1 m, shielded, rg - 58, 50 ? coaxial cable . enter the desired frequency and amplitude from the adc speci - fications tables. typically, most analog devices evaluation boards can accept approximately 2.8 v p - p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow - band, band -p ass filter with 50 ? terminations. good choices of such band - pass filters are available from tte, allen avionics, and k&l microwave, inc . the filter should be connected directly to the evaluation board if possible. output signals the default setup uses th e analog devices, inc., hsc- adc - fpga- 4/hsc - adc -fpga-8 high speed deserialization board to deserialize the digital output data and convert it to parallel cmos. these two channels interface directly with the analog devices standard dual - channel fifo data capture board ( hsc - adc - e va l b - dc ). two of the four channels can then be evaluated at the same time. for more information on the channel settings and optional settings of these boards, visit www.analog.com/fifo . rohde & sch w arz, smhu, 2v p-p signa l synthesizer rohde & sch w arz, smhu, 2v p-p signa l synthesizer band- p ass fi lter xf mr i nput clk ch a to ch d 12-bit serial lvds 2 ch 12-bit parallel cmos usb connection ad9228 ev alu a tion board hsc-adc-fpga-4/ hsc-adc-fpga-8 high speed deserialization board 05727 -014 hsc-adc-evalb-dc fifo data capture board pc running adc analyzer and spi user s oftwa re 1.8v ? + ? + a vdd_dut a vdd_3.3v dr vdd_dut gnd gnd ? + 5.0v gnd a vdd_5v 1.8v 6v dc 2a max w al l outlet 100v t o 240v ac 47hz t o 63hz switching power supply ? + gnd 3.3v ? + 1.5v_fpg a 3.3v_d gnd 3.3v ? + gnd 1.5v ? + vcc gnd 3.3v spi spi spi spi figure 71 . ev aluation board connection
ad9228 rev. d | page 38 of 56 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the ad9228 rev. a evaluation board. ? power: connect the switching power supply that is provided with the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p503. ? ain: the evaluation board is set up for a transformer - coupled analog input with an optimum 50 ? impedance match of 200 mhz of bandwidth (see figure 72 ). for more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. the common mode of the analog inputs is developed from the center tap of the transformer or avdd_dut/2. 0 amplitude (dbfs) frequency (mhz) 05727-088 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 50 100 150 200 250 300 350 400 450 500 ?3d b cutoff = 200mhz figure 72 . evaluation board full - power bandwidth ? vref: vref is set to 1.0 v by tying the sense pin to ground, r237. this causes the adc to operate in 2.0 v p - p full - scale range. a separate external reference option using the adr510 or adr520 is also included on the evaluation board. p opulate r231 and r235 and remove c214. proper use of the vref options is noted in the voltage reference section. ? rbias: rbias has a default setting of 10 k ? (r201) to ground and is used to set the adc core bias current. ? clock: the default clock input circuitry is derived from a simple transformer - coupled circuit using a high bandwidth 1:1 impedance ratio transformer (t201) that adds a very low amount of jitter to the clock path. the clock input is 50 ? terminated and ac - coupled to handle single - ended sine wave types of inputs. the transformer converts the single- ended input to a differential signal that is clipped before entering the adc clock inputs. a differential lvpecl clock can also be used to clock the adc input using the ad9515 (u202). p opulate r225 and r227 with 0 ? resistors and re move r217 and r218 to disconnect the default clock path inputs. in addition, populate c207 and c208 with a 0.1 f capacitor and remove c210 and c211 to disconnect the default clock path outputs. the ad9515 has many pin - strappable options that are set to a default mode of operation . consult the ad9515 data sheet for more information about these and other option s. in addition, an on - board oscillator is available on the osc201 and can act as the primary clock source. the setup is quick and involves installing r212 with a 0 ? resistor and setting the enable jumper (j205) to the on position. if the user wishes to employ a different oscillator, two oscillator footprint options are available (osc201) to check the adc performance. ? pdwn: to enable the power - down feature, short j201 to avdd on the pdwn pin. ? sclk/dtp: to enable the digital test pattern on the digital outputs of the adc, use j204. if j204 is tied to avdd during device po wer - up, test pattern 1000 0000 0000 is enabled. see the sclk/dtp pin section for details. ? sdio/odm: to enable the low power, reduced signal option ( similar to the ieee 1595.3 reduced range link lvds output standard ) , use j203. if j203 is tied to avdd during device power - up, it enables the lvds outputs in a low power, reduced signal option from the default ansi - 644 standard. this option changes the signal swing from 350 mv p - p to 200 mv p - p, reducing the power of the drvdd supp ly. see the sdio/odm pin section for more details. ? csb: to enable processing of the spi inform ation on the sdio and sclk pins , tie j202 low in the always enable mode. to ignore the sdio and sclk information, tie j202 to avdd. ? non - spi mode: for users who wish to operate the dut without using spi, remove jumpers j302, j303, and j304. this disconnects the csb, sclk/dtp, and sdio/o d m pins from the control bus, allowing the dut to operate in its simplest mode. each of these pins has internal termination and will float to its respective level. ? d + x , d ? x : if an alternative data capture method to the setup shown in figure 73 is used, optional receiver terminations, r206 to r211, can be installed next to the high speed back - plane connector.
ad9228 rev. d | page 39 of 56 alternative analog i nput drive c onfiguration the following is a brief description of the alternative analog input drive configuration using the ad8332 dual vga. if this drive option is in use, some components may ne ed to be populated, in which case all the necessary components are listed in table 17 . for more details on the ad8332 dual vga, including how it works an d its optional pin settings, consult the ad8332 data sheet. to configure the analog input to drive the vga instead of the default transformer option, the following components need to be removed and/or changed. ? remove r102, r115, r128, r141, r161, r162, r163, r164, t101, t102, t103, and t104 in the default analog input path. ? populate r101, r114, r127, and r140 with 0 ? resistors in the analog input path. ? populate r105, r113, r118, r124, r131, r137, r151, and r160 with 0 ? resistors in the analog input path to connect the ad8332 . ? populate r152, r153 , r154 , r155, r156, r157, r158, r159, c103, c105, c110, c112, c117, c119, c124, and c126 with 10 k ? resistors to provide an input common - mode level to the adc analog input s. ? remove r305, r306, r313, r314, r405, r406, r412, and r424 to configure the ad8332 . in this configuration, l301 to l308 and l401 to l408 are populated with 0 ? resistors to allow signal connection and use of a filter if ad ditional requirements are necessary.
ad9228 rev. d | page 40 of 56 channel a p101 ain ain vga input connection vga input connection vga input connection vga input connection 1 2 3 6 5 4 t101 cm1 cm1 fb103 10? fb102 10? fb101 10? c104 2.2pf vin_a vin_a p102 dnp cm1 inh1 ch_a avdd_dut ch_a r104 0 ? avdd_dut avdd_dut c106 dnp c107 0.1f c103 dnp c105 dnp c101 0.1f c102 0.1f e101 r161 499? r152 dnp r113 dnp r105 dnp r110 33? r107 dnp r106 dnp r112 1k r111 1k r108 33? r101 dnp r102 64.9 ? r103 0 ? r109 1k channel b p103 ain 1 2 3 6 5 4 t102 cm2 cm2 fb106 10? fb105 10? fb104 10? c111 2.2pf vin_b vin_b p104 dnp cm2 inh2 ch_b avdd_dut ch_b r116 0 ? avdd_dut avdd_dut c113 dnp c114 0.1f c110 dnp c112 dnp c108 0.1f c109 0.1f e102 r162 499? r153 dnp r124 dnp r118 dnp r122 33? r120 dnp r119 dnp r126 1k r125 1k r121 33? r114 dnp r115 64.9 ? r117 0 ? r123 1k channel c p105 ain 1 2 3 6 5 4 t103 cm3 cm3 fb109 10? fb108 10? fb107 10? c118 2.2pf vin_c vin_c p106 dnp cm3 inh3 ch_c avdd_dut ch_c r130 0 ? avdd_dut avdd_dut c120 dnp c121 0.1f c117 dnp c119 dnp c115 0.1f c116 0.1f e103 r163 499? r154 dnp r137 dnp r131 dnp r136 33? r133 dnp r132 dnp r139 1k r138 1k r134 33? r127 dnp r128 64.9 ? r129 0 ? r135 1k channel d p107 ain 1 2 3 6 5 4 t104 cm4 cm4 fb112 10? fb111 10? r143 0 ? c125 2.2pf vin_d vin_d p108 dnp cm4 inh4 ch_d avdd_dut ch_d fb110 10? avdd_dut avdd_dut c127 dnp c128 0.1f c124 dnp c126 dnp r159 dnp c122 0.1f c123 0.1f e104 r164 499? r155 dnp r160 dnp r151 dnp r147 33? r145 dnp r144 dnp r150 1k r149 1k r146 33? r140 dnp r141 64.9 ? r142 0 ? r148 1k r156 dnp r157 dnp 05727-015 ain ain ain r158 dnp dnp: do not populate figure 73 . evaluation board schematic, dut analog inputs
ad9228 rev. d | page 41 of 56 csb c217 0.1f c220 0.1f c221 0.1f c218 0.1f c219 0.1f c223 0.1f c222 0.1f avdd_3.3v clk clkb gnd gnd_pad out0 out0b out1 out1b rset s0 s1 s10 s2 s3 s4 s5 s6 s7 s8 s9 syncb vref vs signal=dnc;27,28 input encode enc enc dnp clock circuit optional clock drive circuit disable enable optional clock oscillator c224 0.1f r214 10k? r215 10k? 14 7 8 1 3 5 12 10 osc201 vfac3h-l c207 0.1f dnp c208 0.1f dnp c209 0.1f dnp c215 0.1f dnp c211 0.1f c210 0.1f e202 1 e201 p201 p203 avdd_3.3v 12 6 7 25 8 16 9 15 10 14 11 13 18 19 23 22 32 1 31 33 u202 signal=avdd_3.3v;4,17,20,21,24,26,29,30 ad9515 3 2 1 cr201 hsms2812 r220 dnp r240 243? r243 100? r241 243? r242 100? 6 5 43 2 1 t201 1 2 3 j205 c205 0.1f c216 0.1f r213 49.9k ? r216 0 ? r221 10k? r212 0 ? dnp r219 dnp s0s1s2s3s4s5s6s7s8s9 s10 opt_clk opt_clk clk avdd_3.3v opt_clk opt_clk clk clk lvpecl output lvds output clk avdd_3.3v 1 1 e203 avdd_3.3v vcc gnd out oe oe' gnd' vcc' out' r244 dnp r245 0 ? s4 s0 s5 s3 s2 s1 avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v r246 dnp r247 0 ? r248 dnp r249 0 ? r250 dnp r251 0 ? r252 dnp r253 0 ? r254 dnp r255 0 ? r256 dnp r257 0 ? s10 s6 s9 s8 s7 avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v r258 dnp r259 0 ? r260 dnp r261 0 ? r262 dnp r263 0 ? r264 dnp r265 0 ? a1 a2 a3 a4 a5 a6 a7 a8 a9 gndab1 gndab10 gndab2 gndab3 gndab4 gndab5 gndab6 gndab7 gndab8 gndab9 gndcd1 gndcd10 gndcd2 gndcd3 gndcd4 gndcd5 gndcd6 gndcd7 gndcd8 gndcd9 header 6469169-1 r205?r211 optional output terminations digital outputs csb3__chb sdi_chb sdo_cha csb2_cha csb1_cha sdi_cha sclk_cha r206 dnp r211 dnp r210 dnp r209 dnp r208 dnp p202 r207 dnp sclk_chb dco c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c10 50 49 48 47 46 45 44 43 42 41 20 19 18 17 16 15 14 13 12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 11 chd chc chb cha fco dco chd chc chb cha fco sdo_chb csb4_chb 40 60 1 9 21 22 4 5 25 6 26 8 31 32 33 34 35 36 37 38 29 10 30 2 23 3 24 28 51 52 53 54 55 56 57 58 39 59 7 27 odm enable clk avdd clk+ clk? d + a d + b d + c d + d d ? a d ? b d ? c d ? d dco+ dco? drvdd drgnd fco+ fco? pdwn rbias refb reft sclk/dtp sdio/odm sense vin + a vin + b vin + c vin + d vin ? a vin ? b vin ? c vin ? d vref avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd drgnd drvdd reference decoupling c204 0.1f c203 0.1f c202 2.2f c201 0.1f r205 10k? r203 100k? r204 100k? 3 2 1 j201 1 8 7 30 20 18 16 14 19 17 15 13 24 23 11 12 22 21 10 2 25 26 27 32 35 36 39 45 46 5 6 9 31 40 43 44 28 29 41 33 38 47 4 34 37 48 3 42 u201 ad9228lfcsp r202 100k? csb_dut 1 2 3 j202 sdio_odm 1 2 3 j203 sclk_dtp 3 2 1 j204 drvdd_dut drvdd_dut r201 10k? avdd_dut cha chb chc chd cha chb chc dco dco fco fco avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut vsense_dut vin_a vin_b vin_c vin_a vin_b vref_dut avdd_dut avdd_dut clk chd avdd_dut avdd_dut avdd_dut avdd_dut avdd_dut vin_d vin_c vin_d gnd gnd avdd_dut pwdn enable always enable spi dtp enable u203 cw vref = 1v vref = external vref = 0.5v remove c214 when using external vref vref = 0.5v(1+r232/r233) vref select reference circuit c212 0.1f r229 4.99k ? c214 1f c213 0.1f r230 10k? r231 dnp dnp vsense_dut r228 470k? dnp dnp r234 dnp r235 dnp r236 dnp r237 0 ? dnp avdd_dut vref_dut avdd_dut trim/nc v? v+ adr510/20 1v r232 dnp r233 dnp r217 0 ? r218 0 ? r225 0 ? dnp r226 49.9 ? dnp r227 0 ? dnp r238 dnp r239 10k? c206 0.1f r223 0 ? r224 0 ? r222 4.12k ? 2 3 5 nc = no connect r266 100k ? - dn p r267 100k ? - dn p clip sine out (default) dnp: do not populate optional ext ref figure 74 . evaluation board schematic, dut, vref, clock inputs, and digital output interface
ad9228 rev. d | page 42 of 56 cw power down enable (0-1v = disable power) external variable gain drive variable gain circuit (0-1.0v dc) r 319 10k? 1 2 jp 301 gnd vg r 320 39k? vg avdd_5v hilo pin hi gain range = 2.25v-5.0v lo gain range = 0-1.0v r 315 10k? l 310 120nh c 322 0.018 f c 317 0.018 f r 316 274? r 317 274? c 312 0.1f c 325 0.1f c 313 0.1f c 314 0.1f l 309 120nh c 318 22 pf c 321 0.1f c 320 0.1f c 316 0.1f r 318 10k c 323 22 pf c 319 0.1f c 324 0.1f i nh 4 i nh 3 avdd_5v avdd_5v c 326 10 f c 315 10 f optional vga drive circuit for channel c and channel d c 311 0.1f r312 10k r 313 10k dn p c 303 dn p l 304 0 r 303 dn p l 308 0 24 17 20 23 18 22 19 21 r 304 dn p l 306 0 l 305 0 l 302 0 l 303 0 l 307 0 c 308 0.1f c 307 0.1f c 306 0.1f c 305 0.1f r 310 187? r 309 187 r 308 187 r 307 187 c 302 dn p l 301 0 c 301 dn p r 305 374 r 306 374 ch_c ch_d ch_d ch_c avdd_5v avdd_5v avdd_5v c 304 dn p r 301 dn p r 302 dn p 31 10 26 25 14 27 3 6 4 5 1 8 32 9 15 16 vg 28 13 29 12 30 11 2 7 com1 com2 enb l enb v gain hilo inh1 inh2 lmd1 lmd2 lon1 lon2 lop1 lop2 mode nc rc lmp vcm1 vcm2 vin1 vin2 vip1 vip2 voh1 voh2 vol1 vol2 vps1 vps2 vpsv ad833 2 comm comm r311 10k? dn p r 314 10k? dn p c 310 0.1f c 309 1000pf rclamp pin hilo pin = lo = 50mv hilo pin = h = 75mv 05727-017 mode pin positive gain slope = 0-1.0v negative gain slope = 2.25v-5.0v u 301 populate l 301- l 308 with 0 ? resistors or des ig n yo ur own fi lt er. dnp: do not populate figure 75 . evaluation board schematic, optional dut analog input drive and spi interface circuit
ad9228 rev. d | page 43 of 56 mode pin positive gain slope = 0-1.0v negative gain slope = 2.25v-5.0v hilo pin hi gain range = 2.25v-5.0v lo gain range = 0-1.0v r414 10k? l410 120nh c420 0.018f c415 0.018f r415 274? c410 0.1f c425 0.1f c423 0.1f c424 0.1f l409 120nh c418 22pf c417 0.1f c416 0.1f c414 0.1f r417 10k c421 22pf c419 0.1f c422 0.1f inh2 inh1 avdd_5v avdd_5v c426 10f c413 10f optional vga drive circuit for channel a and channel b c409 0.1f r411 10k r412 10k dnp c403 dnp l404 0 ? r403 dnp l408 0 ? 24 17 20 23 18 22 19 21 r404 dnp l406 0 ? l405 0 ? l402 0 ? l403 0 ? l407 0 ? c408 0.1f c407 0.1f c406 0.1f c405 0.1f r410 187? r409 187 r408 187 r407 187 c402 dnp l401 0 ? c401 dnp r405 374 r406 374 ch_a ch_b ch_b ch_a avdd_5v avdd_5v avdd_5v c404 dnp r401 dnp r402 dnp 31 10 26 25 14 27 3 6 4 5 1 8 32 9 15 16 vg 28 13 29 12 30 11 2 7 com1 com2 enbl enbv gain hilo inh1 inh2 lmd1 lmd2 lon1 lon2 lop1 lop2 mode nc rclmp vcm1 vcm2 vin1 vin2 vip1 vip2 voh1 voh2 vol1 vol2 vps1 vps2 vpsv ad8332 u401 comm comm r413 10k? dnp r424 10k? dnp c412 0.1f c411 1000pf rclamp pin hilo pin = lo = 50mv hilo pin = h = 75mv 05727-018 power down enable (0?1v = disable power) r416 274? populate l 401- l 408 with 0 ? resistors or des ig n yo ur own fi lt er. y1 vcc y2 a2 gnd a1 spi circuitry from fifo sdio_odm avdd_dut r431 1k? r432 1k? r433 1k? avdd_3.3v 1 2 3 4 5 6 nc7wz07 u403 r425 10k? avdd_dut reset/reprogram 1 2 3 4 s401 +3.3v = normal operation = avdd_3.3v +5v = programming = avdd_5v avdd_5v avdd_3.3v j402 c427 0.1f r418 4.75k ? pic12f629 r419 261 4 3 1 2 5 6 8 7 u402 cr401 gp0 gp1 gp2 gp4 gp5 vdd vss mclr/ gp3 remove when using or programming pic (u402) r427 0 ? r420 0 ? r428 0 ? r426 0 ? sdo_cha sdi_cha sclk_cha csb1_cha c429 0.1f sclk_dtp csb_dut avdd_dut y1 vcc y2 a2 gnd a1 1 2 3 4 5 6 u404 r430 10k? r429 10k? nc7wz16 c428 0.1f pic programming header mclr/gp3 gp0 gp1 picvcc mclr/gp3 gp0 gp1 picvcc 9 7 5 3 1 10 8 6 4 2 j401 e401 r421 0-dnp r423 0-dnp r422 0-dnp optional dnp: do not populate figure 76 . evaluation board schematic, optional dut analog input drive and spi interface circuit (continued)
ad9228 rev. d | page 44 of 56 mounting holes connected to ground h2 h3h1 h4 p1 p2 p3 p4 p5 p6 p7 p8 optional power input +5.0v +1.8v +1.8v +3.3v 1 2 3 4 5 6 7 8 p501 3.3v_avdd 5v_avdd l502 10h dut_avdd dut_drvdd c509 0.1f c508 10f l503 10h l501 10h drvdd_dut avdd_dut 0.1f c505 0.1f c507 c503 0.1 f av dd_5v 10f c504 c502 10f 10f c506 avdd_3.3v 10h l508 decoupling capacitors avdd_3.3v 0.1f c524 0.1f c525 c521 0.1f c531 0.1 f c530 0. 1f c529 0.1f c522 0.1f c528 0.1f c527 0.1f c526 0.1f 0.1f c517 0.1f c516 c518 0.1f c520 0.1f c519 0.1f c523 0.1f drvdd_dut avdd_dut avdd_5v smdc110f power supply input 6v, 2v maximum 1 3 2 p503 c501 10f f501 d502 3a shot_rect do-214ab d501 s2a_rect 2a do-214aa 2 1 3 4 fer501 choke_coil cr501 r501 261? pwr_in + gnd input output1 gnd input output1 output4 output4 gnd input gnd input dnp: do not populate 4 2 3 1 adp3339akc-5 u504 4 2 3 1 adp3339akc-3.3 u502 1 3 2 4 u501 adp3339akc-1.8 1 3 2 4 u503 adp3339akc-1.8 l505 10h 10h l504 c515 1f c513 1f c512 1f c514 1f pwr_in pwr_in dut_avdd dut_drvdd 5v_avdd 3.3v_avdd pwr_in pwr_in c532 1f c534 1f c535 1f c533 1f l507 10h l506 10h output1 output1 output4 output4 05727-019 figur e 77 . evaluation board schematic, power supply inputs
ad9228 rev. d | page 45 of 56 05727-020 figure 78 . evaluation board layout, primary side
ad9228 rev. d | page 46 of 56 05727-021 figure 79 . evaluation board layout, ground plane
ad9228 rev. d | page 47 of 56 05727-022 figure 80 . evaluation board layout, power plane
ad9228 rev. d | page 48 of 56 05727-023 figure 81 . evaluation board layout, secondary side (mirrored image)
ad9228 rev. d | page 49 of 56 table 17 . evaluation board bill of materials (bom) 1 item q ty. reference designator device package value manufacturer manufacturers part number 1 1 ad9228lfcsp_reva pcb pcb pcb 2 75 c101, c102, c107, c108, c109, c114, c115, c116, c121, c122, c123, c128, c201, c203, c204, c205, c206, c210, c211, c212, c213, c216, c217, c218, c219, c220, c221, c222, c223, c224, c310, c311, c312, c313, c314, c316, c319, c320, c321, c324, c325, c409, c410, c412, c414, c416, c417, c419, c422, c423, c424, c425, c427, c428, c429, c503, c505, c507, c509, c516, c517, c518, c519, c520, c521, c522, c523, c524, c525, c526, c527, c528, c529, c530, c531 capacitor 402 0.1 f, ceramic, x5r, 10 v, 10% tol murata grm155r71c104ka88d 3 4 c104, c111, c118, c125 capacitor 402 2.2 pf, ceramic, cog, 0.25 pf tol, 50 v murata grm1555c1h2r2gz01b 4 4 c315, c326, c413, c426 cap acitor 805 10 f, 6.3 v 10% ceramic, x5r murata grm219r60j106ke19d 5 1 c202 capacitor 603 2.2 f, ceramic, x5r, 6.3 v, 10% tol murata grm188c70j225ke20d 6 2 c309, c411 capacitor 402 1000 pf, ceramic, x7r, 25 v, 10% tol murata grm155r71h102ka01d 7 4 c31 7, c322, c415, c420 capacitor 402 0.018 f, ceramic, x7r, 16 v, 10% tol avx 0402yc183kat2a 8 4 c318, c323, c418, c421 capacitor 402 22 pf, ceramic, npo, 5% tol, 50 v murata grm1555c1h220jz01d 9 1 c501 capacitor 1206 10 f, tantalum, 16 v, 20% tol rohm tc a1c106m8r 10 9 c214, c512, c513, c514, c515, c532, c533, c534, c535 capacitor 603 1 f, ceramic, x5r, 6.3 v, 10% tol murata grm 188r61c105ka93d 11 8 c305, c306, c307, c308, c405, c406, c407, c408 capacitor 805 0.1 f, ceramic, x7r, 50 v, 10% tol murata gr m21br71h104ka01l 12 4 c502, c504, c506, c508 capacitor 603 10 f, ceramic, x5r, 6.3 v, 20% tol murata grm188r60j106m 13 1 cr201 diode sot -23 30 v, 20 ma, dual schottky agilent technologies hsms2812- trig 14 2 cr401, cr501 led 603 green, 4 v, 5 m candela panasonic lnj314g8tra 15 1 d502 diode do - 214ab 3 a, 30 v, smc micro commercial co. sk33- tp 16 1 d501 diode do - 214aa 2 a, 50 v, smc micro commercial co. s2a- tp
ad9228 rev. d | page 50 of 56 item q ty. reference designator device package value manufacturer manufacturers part number 17 1 f501 fuse 1210 6.0 v, 2.2 a trip - current resettable fuse tyco/raychem nanosmdc110f-2 18 1 fer501 choke c oil 2020 10 h, 5 a, 50 v , 190 ? @ 100 mhz murata dl w5bsn191sq2l 19 12 fb101, fb102, fb103, fb104, fb105, fb106, fb107, fb108, fb109, fb110, fb111, fb112 ferrite bead 603 10 ? , test freq 100 mhz, 25% tol, 500 ma murata bl m18ba100sn1b 20 1 jp301 connector 2- pin 10 0 mil header jumper, 2 - pin samtec tsw -102-07-g-s 21 2 j205, j402 connector 3- pin 100 mil header jumper, 3 - pin samtec tsw -103-07-g-s 22 1 j201 to j204 connector 12- pin 100 mil header male, 4 3 triple row straight samtec tsw -104-08-g-t 23 1 j401 connector 10- pin 100 mil header, male, 2 5 double row straight samtec tsw -105-08-g-d 24 8 l501, l502, l503, l504, l505, l506, l507, l508 ferrite bead 1210 10 h, bead core 3.2 2.5 1.6 smd, 2 a murata blm31pg500sn1l 25 4 l309, l310, l409, l410 inductor 402 120 nh, test freq 100 mhz, 5% tol, 150 ma murata lqg15hnr12j02b 26 16 l301, l302, l303, l304, l305, l306, l307, l308, l401, l402, l403, l404, l405, l406, l407, l408 resistor 805 0 ? , 1/8 w, 5% tol nic compo nents nrc10zotrf 27 1 osc201 oscillator smt clock oscillator, 65.00 mhz, 3.3 v valpey fisher vfac3h-l- 65mhz 28 5 p101, p103, p105, p107, p201 connector sma side - mount sma for 0.063" board thickness johnson components 142-0710-851 29 1 p202 connector header 1469169- 1, right angle 2 - pair, 25 mm, header assembly tyco 6469169-1 30 1 p503 connector 0.1", pcmt sc1153, power supply connector switchcraft rapc722x 31 15 r201, r205, r214, r215, r221, r239 , r312, r315, r318, r411, r414, r417, r425, r429, r430 resistor 402 10 k ? , 1/16 w, 5 % tol nic compo nents nrc04j103trf 32 14 r103, r117, r129, r142, r216, r217, r218, r223, r224, r237, r420, r426, r427, r428 resistor 402 0 ? , 1/16 w, 5% tol nic compo nents nrc04z0trf 33 4 r102, r115, r128, r141 resistor 402 64.9 ? , 1/16 w, 1% to l nic compo nents nrc04f64r9trf 34 4 r104, r116, r130, r143 resistor 603 0 ? , 1/10 w, 5% tol nic compo nents nrc06z0trf
ad9228 rev. d | page 51 of 56 item q ty. reference designator device package value manufacturer manufacturers part number 35 15 r109, r111, r112, r123, r125, r126, r135, r138, r139, r148, r149, r150, r431, r432, r433 resistor 402 1 k ? , 1/16 w, 1% tol nic compo nents nrc04f1001trf 36 8 r108, r110, r121, r122, r134, r136, r146, r147 resistor 402 33 ? , 1/16 w, 5% tol nic compo nents nrc04j330trf 37 4 r161, r162, r163, r164 resistor 402 499 ? , 1/16 w, 1% tol nic compo nents nrc04f4990trf 38 3 r202, r2 03, r204 resistor 402 100 k ? , 1/16 w, 1% tol nic compo nents nrc04f1003trf 39 1 r222 resistor 402 4.12 k ? , 1/16 w, 1 % tol nic compo nents nrc04f4121trf 40 1 r213 resistor 402 49.9 ? , 1/16 w, 0.5% t ol susumu rr 0510r- 49r9 -d 41 1 r229 resistor 402 4.99 k ? , 1/16 w, 5% tol nic compo nents nrc04f4991trf 42 2 r230, r319 potentiometer 3- lead 10 k ? , c ermet trimmer potentiometer, 18- turn top adjust, 10%, 1/2 w bc componen ts ct 94ew 103 43 1 r228 resistor 402 470 k ? , 1/16 w, 5 % tol nic compo nents nrc04j474trf 44 1 r320 resistor 402 39 k ? , 1/16 w, 5 % tol nic compo nents nrc04j393trf 45 8 r307, r308, r309, r310, r407, r408, r409, r410 resistor 402 187 ? , 1/16 w, 1% tol nic compo nents nrc04f1870trf 46 4 r305, r306, r405, r406 resistor 402 374 ? , 1/16 w, 1% tol nic compo nents nrc04f3740trf 47 4 r316, r317, r415, r416 resistor 402 274 ? , 1/16 w, 1% tol nic compo nents nrc04f2740trf 48 11 r245, r247, r249, r251, r253, r255, r257, r259, r261, r263, r265 resistor 201 0 ? , 1/20 w, 5% tol panasonic er j -1ge0r00c 49 1 r418 resistor 402 4.75 k ? , 1/16 w, 1 % tol nic compo nents nrc04j472trf 50 1 r419 resistor 402 261 ? , 1/16 w, 1% tol nic compo nents nrc0 4f2610 trf 51 1 r501 resistor 603 261 ? , 1/16 w, 1% tol nic compo nents nrc06f2610 trf 52 2 r240, r241 resistor 402 243 ? , 1/16 w, 1% tol nic compo nents nrc04f2430trf 53 2 r242, r243 resistor 402 100 ? , 1/16 w, 1% tol nic compo nents nrc04f1000trf 54 1 s401 switch smd light touch , 100ge, 5 mm panasonic evq - plda15 55 5 t101, t102, t103, t104, t201 transformer cd542 adt1 -1w t, 1:1 impedance ratio transformer mini - circuits adt1 -1wt+ 56 2 u501, u503 ic sot -223 adp33339akc - 1.8, 1.5 a, 1.8 v ldo regulator analog devices adp33339akcz-1.8
ad9228 rev. d | page 52 of 56 item q ty. reference designator device package value manufacturer manufacturers part number 57 2 u301, u401 ic lfcsp, cp-32 ad8332acp, ultralow noise precision dual vga analog devices ad8332acpz 58 1 u504 ic sot -223 adp333 9akc -5 analog devices adp33 39akcz-5 59 1 u502 ic sot -223 adp33 39akc-3.3 analog devices adp3 339akcz-3.3 60 1 u201 ic lfcsp, cp-48-1 ad9228 bcpz -65, quad, 12 - bit, 65 msps serial lvds 1.8 v adc analog devices ad9228bc pz -65 61 1 u203 ic sot -23 adr510ar tz , 1.0 v, precision low noise shunt voltage reference analog devices adr510artz 62 1 u202 ic lfcsp cp-32-2 ad9515 bcpz analog devices ad9515bcpz 63 1 u403 ic sc70, maa06a nc7wz07 fairchild nc7wz07p6x_nl 64 1 u404 ic sc70, maa06a nc7wz16 fairchild nc7wz16p6x_nl 65 1 u402 ic 8- soic flash prog mem 1k 14, ram size 64 8, 20 mhz speed, pic12f controller series microchip pic12f629- i/sn 1 this bom is rohs compliant.
ad9228 rev. d | page 53 of 56 outline dimensions * compliant to jedec standards mo-220-vkkd-2 with exception to exposed pad dimension. forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 48 12 13 37 36 24 25 * 5.55 5.50 sq 5.45 0.50 0.40 0.30 0.30 0.23 0.18 0.80 max 0.65 typ 5.50 ref coplanarity 0.08 exposed pad (bottom view) 0.20 ref 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 12 max top view 0.60 max 0.60 max pin 1 indicator 0.50 ref pin 1 indicator 0.22 min 7.10 7.00 sq 6.90 6.85 6.75 sq 6.65 02-23-2010-c figure 82. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9228abcpz-40 2 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9228abcpzrl7-40 2 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9228abcpz-65 2 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9228abcpzrl7-65 2 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-8 ad9228-65ebz evaluation board 1 z = rohs compliant part. 2 reference pcn 09_0156.
ad9228 rev. d | page 54 of 56 notes
ad9228 rev. d | page 55 of 56 notes
ad9228 rev. d | page 56 of 56 notes ? 2006 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05727 -0- 4 /10(d)

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